The Failure Mechanism of High Voltage Tolerance IO Buffer under ESD

In this paper, the real-time IV measurement and TCAD simulation were used to study why the ESD performance of the HVT IO circuit is different from the ST NMOS device. The real-time IV measurement shows that top gate induced voltage of the ST NMOS in HVT IO circuit under ESD zapping event is much higher than the ST NMOS device. The simulation shows that high gate voltage will induce the c w e n t crowded in the channel region, so as to degrade the device ESD perfomnce. This phenomenon is called as “gate voltage-induced current crowding” (CVICC) effect. However, it is also found with non-silicide S I D shllcmc and increasing the W O dimension at the drain region of top NMOSFET can effectively reduce the CVlCC effect and push the currents to flow through bulk parasitic bipolar transistor. As a result, ESD failure threshold can be much improved.